This invention relates to a substrate bias generator for producing a potential in a semiconductor substrate, and more particularly to such a generator used with an integrated circuit including, as the fundamental elements, insulated gate type MOS field effect transistors and especially used with a dynamic circuit.
Conventional substrate bias generators have comprised an MOS capacitor and one pair of serially connected MOSFET's (which is the abbreviation for MOS field effect transistors) with each gate electrode connected to the associated drain electrode disposed on one of the opposite main faces of the P.sup.- type semiconductor substrate and interconnected so that the MOS capacitor is connected to the junction of the MOSFET's and one of the MOSFET's has a source electrode which is normally placed at a ground potential while the other MOSFET has its drain electrode connected to an electrode on the other main face of the substrate. Therefore, parasitic diodes are formed between a pair of N.sup.+ type semiconductor regions respectively forming an electrode for the MOS capacitor and a combined drain and source region of both MOSFET's and the substrate, while those regions and the substrate have parasitic capacitances to ground.
With a voltage in the form of a square pulse applied to the MOS capacitor so as to place the substrate bias generator in operation, electrons due to an electric charge on the parasitic capacitor associated with the substrate are injected into the substrate through the parasitic diodes, on the one hand, and through the other MOSFET and the other main face of the substrate, on the other hand. That portion of the electrons passed through the parasitic diodes are soon recombined with holes forming majority carriers within the substrate to disappear while that portion thereof passed through the MOSFET are instantaneously recombined with holes on a portion of the other main face of the substrate contacting the electrode thereon. Therefore, a shortage of holes is developed in the substrate resulting in the generation of a negative potential in the substrate. This substrate potential is developed on the electrode on the other main face of the substrate.
Conventional substrate bias generators such as described above have been difficult to be used with the dynamic memory cell in the form of an integrated circuit disposed on the same semiconductor chip as the generator. It is assumed that the dynamic memory cell includes a single MOSFET and a single MOS capacitor serially connected to each other and stores data expressed by a binary ONE by having the MOS capacitor charged to a high potential. Under these assumed conditions, some of the electrons passed through the parasitic diodes in a mating substrate bias generator might be captured by the MOS capacitor in the cell. As a result, the MOS capacitor changes from the high potential to a low potential which may reach a ground potential corresponding to a binary ZERO as the case may be. This has resulted in a malfunction of the dynamic memory cell so that a binary ZERO is read out although a binary ONE should have been written in the cell. Therefore, conventional substrate bias generators have disadvantages in that mating dynamic circuits may malfunction.
Accordingly, it is an object of the present invention to provide a new and improved substrate bias generator for producing a potential in a semiconductor substrate disposed in an integrated circuit on a semiconductor chip so as to permit a very small number of electrons to be injected into an associated semiconductor substrate to thereby minimize the probability of malfunctioning in a dynamic circuit integrated on the same chip as the generator.